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2-wire serialflash with block lock tm protection 128k 16k x 8 bit xicor, 1995, 1996 patents pending characteristics subject to change without notice 7012-0.5 8/7/96 t2/c0/d16 sh 1 X24F128 functional diagram features 1.8v to 3.6v or 5v ?nivolt read and program power supply versions low power cmos ?ctive read current less than 1ma ?ctive program current less than 3ma ?tandby current less than 1 m a 100khz 2-wire serial interface internally organized 16k x 8 extended temperature range ?0 c to +85 c 32 byte sector program mode ?inimizes total program time per byte programmable block lock protection ?lock lock (0, 1/4, 1/2, or all of serialflash) ?oftware program protection ?rogrammable hardware program protect bidirectional data transfer protocol self-timed program cycle ?ypical program cycle time of 5ms high reliability ?ndurance: 100,000 cycles ?ata retention: 100 years available packages ?-lead dip ?6-lead soic description the X24F128 is a cmos serialflash memory, inter- nally organized 16k x 8. the device features a serial interface and software protocol allowing operation on a simple two wire bus. three device select inputs (s 0 ? 2 ) allow up to eight devices to share a common two wire bus. a program protect register at the address location ffffh provides three program protection features: software program protect, block lock protect, and hardware program protect. the software program protect feature prevents any nonvolatile writes to the device until the pel bit in the program protect register is set. the block lock protection feature allows the user to individually block protect four blocks of the array by programming two bits in the program protect register. the programmable hardware program protect feature allows the user to install the device with pp tied to v cc , program the entire memory array in circuit, and then enable the hardware program protection by programming a ppen bit in the program protect register. after this, selected blocks of the array, including the program protect register itself, are permanently protected from being erased. scl serialflash data and address (sda) pp program voltage control serialflash array 16k x 8 s1 s0 s2 4k x 8 4k x 8 8k x 8 command decode and control logic sector decode logic device select logic program protect register block lock and program protect control logic y decode logic data register 7012 ill f01.4 a pplication n ote a v a i l a b l e an84
X24F128 2 xicor serialflash memories are designed and tested for applications requiring extended endurance. inherent data retention is greater than 100 years. pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the pull- up resistor selection graph at the end of this data sheet. device select (s 0 , s 1 , s 2 ) the device select inputs (s 0 , s 1 , s 2 ) are used to set the ?st three bits of the 8-bit slave address. this allows up to eight devices to share a common bus. these inputs can be static or actively driven. if used statically they must be tied to v ss or v cc as appro- priate. if actively driven, they must be driven with cmos levels. program protect (pp) the program protect input controls the hardware program protect feature. when held low, hardware program protection is disabled and the device can be programmed normally. when this input is held high, and the ppen bit in the program protect register is set high, program protection is enabled, and nonvola- tile writes are disabled to the selected blocks as well as the program protect register itself. pin names 7012 frm t01 pin configuration symbol description s 0 , s 1 , s 2 device select inputs sda serial data scl serial clock pp program protect v ss ground v cc supply voltage nc no connect v cc pp scl sda s 0 s 1 s 2 v ss 1 2 3 4 8 7 6 5 8-lead dip 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16-lead soic s 0 s 1 nc nc nc nc s 2 v ss v cc pp nc nc nc nc scl sda X24F128 X24F128 7012 ill f02.1
X24F128 3 device operation the device supports a bidirectional, bus oriented protocol. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data trans- fers, and provide the clock for both transmit and receive operations. therefore, the X24F128 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. scl sda data stable data change 7012 ill f03 scl sda start bit stop bit 7012 ill f04 figure 1. data validity figure 2. definition of start and stop
X24F128 4 figure 3. acknowledge response from receiver stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3. the device will respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a program operation have been selected, the device will respond with an acknowledge after the receipt of each subsequent byte. in the read mode the device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. if an acknowledge is not detected, the device will terminate further data trans- missions. the master must then issue a stop condition to return the device to the standby power mode and place the device into a known state. 7012 ill f05 scl from master data output from transmitter 1 89 data output from receiver start acknowledge
X24F128 5 figure 4. device addressing 1 s 1 s 0 r/w device select 01 0 s 2 0 a10 a9 a8 0 a13 high order address a12 a11 device type identifier slave address byte d7 d2 d1 d6 d5 d4 d3 data byte address byte 1 a2 a1 a0 a5 low order address a4 a3 address byte 0 a7 a6 d0 7012 ill f06.1 device addressing following a start condition, the master must output the address of the slave it is accessing. the ?st four bits of the slave address byte are the device type identi?r bits. these must equal ?010? the next 3 bits are the device select bits s 0 , s 1 , and s 2 . this allows up to 8 devices to share a single bus. these bits are compared to the s 0 , s 1 , and s 2 device select input pins. the last bit of the slave address byte de?es the operation to be performed. when the r/w bit is a one, then a read operation is selected. when it is zero then a program operation is selected. refer to ?ure 4. after loading the slave address byte from the sda bus, the device compares the device type bits with the value ?010 and the device select bits with the status of the device select input pins. if the compare is not successful, no acknowledge is output during the ninth clock cycle and the device returns to the standby mode. the byte address is either supplied by the master or obtained from an internal counter, depending on the operation. when required, the master must supply the two address bytes as shown in ?ure 4. the internal organization of the e 2 array is 512 sectors by 32 bytes per sector. the sector address is partially contained in the address byte 1 and partially in bits 7 through 5 of the address byte 0. the speci? byte address is contained in bits 4 through 0 of the address byte 0. refer to ?ure 4.
X24F128 6 figure 5. sector program sequence programming operations sector program operation the device executes a thirty-two byte sector program operation. for a sector program operation, the device requires the slave address byte, address byte 1, and address byte 0. address byte 0 must contain the ?st byte of the sector to be programmed. upon receipt of address byte 0, the device responds with an acknowl- edge, and waits for the ?st eight bits of data. after receiving the 8 bits of the ?st data byte, the device again responds with an acknowledge. the device will respond with an acknowledge after the receipt of each of 31 more bytes. each time the byte address is inter- nally incremented by one, while the sector address remains constant. when the counter reaches the end of the sector, the master terminates the data loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. all inputs are disabled until completion of the nonvolatile write cycle. the sda pin is at high impedance. refer to ?ure 5 for the address, acknowledge, and data transfer sequence. s t a r t slave address s t o p a c k a c k a c k a c k a c k 7012 ill f08.1 data (1) signals from the master sda bus signals from the slave data (32) address byte 1 address byte 0 1 0 1 0 0 s p
X24F128 7 acknowledge polling the maximum program cycle time can be signi?antly reduced using acknowledge polling. to initiate acknowledge polling, the master issues a start condi- tion followed by the slave address byte for a program or read operation. if the device is still busy with the nonvolatile write cycle, then no ack will be returned. if the device has completed the nonvolatile write opera- tion, an ack will be returned and the host can then proceed with the read or program operation. refer to ?ure 6. 7012 ill f09 byte load completed by issuing stop. enter ack polling issue start issue slave address byte (read or program) ack returned? nonvolatile write cycle complete. continue sequence? continue normal read or program command sequence proceed issue stop no yes yes issue stop no read operations read operations are initiated in the same manner as program operations with the exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, random reads, and sequential reads. current address read internally, the device contains an address counter that maintains the address of the last byte read or programmed, incremented by one. after a read opera- tion from the last address in the array, the counter will ?oll over to the ?st address in the array. after a program operation to the last address in a given sector, the counter will ?oll over to the ?st address of the same sector. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the byte at the current address. the master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. refer to ?ure 7 for the address, acknowledge, and data transfer sequence. it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. s t a r t slave address s t o p a c k data 7012 ill f10 signals from the master sda bus signals from the slave 1010 1 sp figure 6. acknowledge polling sequence figure 7. current address read sequence
X24F128 8 random read random read operation allows the master to access any memory location in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must ?st perform a ?ummy program opera- tion. the master issues the start condition and the slave address byte with the r/w bit low, receives an acknowledge, then issues address byte 1, receives another acknowledge, then issues address byte 0 containing the address of the byte to be read. after the device acknowledges receipt of address byte 0, the master issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge and then eight bits of data from the device. the master terminates the read oper- ation by not responding with an acknowledge and then issuing a stop condition. refer to ?ure 8 for the address, acknowledge, and data transfer sequence. the device will perform a similar operation called ?et current address if a stop is issued instead of the second start shown in ?ure 9. the device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. the effect of this oper- ation is that the new address is loaded into the address counter, but no data is output by the device. the next current address read operation will read from the newly loaded address. sequential read sequential reads can be initiated as either a current address read or random read. the ?st byte is trans- mitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. the device continues to output data for each acknowledge received. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all byte addresses, allowing the entire memory contents to be read during one operation. at the end of the address space the counter ?olls over to address 0000h and the device continues to output data for each acknowledge received. refer to ?ure 9 for the acknowledge and data transfer sequence. slave address s s t o p a c k a c k a c k a c k data (1) 7012 ill f12.1 data (2) signals from the master sda bus signals from the slave data (n?) data (n) 1 p signals from the master sda bus signals from the slave s t a r t slave address s t o p a c k a c k a c k address byte 1 slave address 7012 ill f11.1 1 0 1 0 0 address byte 0 s t a r t 1 data a c k s p s figure 8. random read sequence figure 9. sequential read sequence
X24F128 9 program protect register (ppr) register program operation the program protect register can only be modi?d by programming one data byte directly to the address ffffh as described below. the data byte must contain zeroes where indicated in the procedural descriptions below; otherwise the oper- ation will not be performed. only one data byte is allowed for each register program operation. the part will not acknowledge any data bytes after the ?st byte is entered. the user then has to issue a stop to initiate the nonvolatile write cycle that programs bl0, bl1, and ppen to the nonvolatile bits. a stop must also be issued after volatile register program opera- tions to put the device into standby. the state of the program protect register can be read by performing a random read at ffffh at any time. the part will reset itself after the ?st byte is read. the master should supply a stop condition to be consistent with the protocol. after the read, the address counter contains 0000h. program protect register: ppr (addr = ffff h ) pel: program enable latch (volatile) 0 = pel reset, programming disabled. 1 = pel set, programming enabled. rpel: register program enable latch (volatile) 0 = rpel reset, programs to the program protect register disabled. 1 = rpel set, programs to the program protect register enabled. bl0, bl1: block lock protect bits (nonvolatile) the block lock protect bits, bl0 and bl1, determine which blocks of the array are protected. a program to a protected block of memory is ignored, but will receive an acknowledge. the master must issue a stop to put the part into standby, just as it would for a valid program; but the stop will not initiate an internal nonvolatile write cycle. see ?ure 10. ppen: program protect enable bit (nonvolatile) the program protect (pp) pin and the program protect enable (ppen) bit in the program protect register control the programmable hardware program protection feature. hardware program protection is enabled when the pp pin is high and the ppen bit is high, and disabled when either the pp pin is low or the ppen bit is low. when the chip is hardware program protected, nonvolatile writes are disabled to the program protect register, including the block lock protect bits and the ppen bit itself, as well as to the block lock protected sections in the memory array. only the sections of the memory array that are not block lock protected, and the volatile bits pel and rpel, can be programmed. note that since the ppen bit is program protected, it cannot be changed back to a low state; so program protection is enabled as long as the pp pin is held high. figure 11 de?es the program protect status for each combination of ppen and pp. unused bit positions bits 0, 5 & 6 are not used. all programs to the ppr must have zeros in these bit positions. the data byte output during a ppr read will contain zeros in these bits. programming the pel and rpel bits pel and rpel are volatile latches that power up in the low (disabled) state. while the pel bit is low, program operations to any address other than ffffh will be ignored (no acknowledge will be issued after the data byte). the pel bit is set by programming 00000010 to address ffffh. once set, pel remains high until either it is reset to 0 (by programming 00000000 to ffffh) or until power cycles. program- ming pel and rpel does not cause a nonvolatile write cycle, so the device is ready for the next opera- tion immediately after the stop condition. the rpel bit controls programming to the block lock protect bits, bl0 and bl1, and the ppen bit. if rpel is 0 then no programming operations can be performed on bl0, bl1, or ppen. rpel is reset when power cycles or after any nonvolatile write, including those to the block lock protect bits, the ppen bit, or any sector in the memory array. rpel must be reset before pel can be reset. rpel and pel cannot be reset in one program operation. rpel can also be reset by programming u00xy010 to ffffh only when the ppr is not protected. this is the same operation as in step 3 described below, and will result 7 6543 2 10 ppen 0 0 bl1 bl0 rpel pel 0
X24F128 10 programming to the bl and ppen bits a 3 step sequence is required to change the nonvola- tile block lock protect or program protect enable bits: 1) set pel=1, program 00000010 to address ffffh (volatile write cycle.) 2) set rpel=1, program 00000110 to address ffffh (volatile write cycle.) 3) set bl1, bl0, and/or ppen bits, program u00xy010 to address ffffh, where u=ppen, x=bl1, and y=bl0. (nonvolatile write cycle.) the three step sequence was created to make it dif? cult to change the contents of the program protect register accidentally. if pel was set to one by a previous register program operation, the user may start at step 2. rpel is reset to zero in step 3 so that user is required to perform steps 2 and 3 to make another change. rpel must be 0 in step 3. if the rpel bit in the data byte for step 3 is a one, then no changes are made to the program protect register and the device remains at step 2. the pp pin must be low or the ppen bit must be low before a nonvolatile register program operation is initiated. otherwise, the program operation will abort and the device will go into standby mode after the master issues the stop condition in step 3. step 3 is a nonvolatile write operation, requiring 10ms max to complete (acknowledge polling may be used to reduce this time requirement). it should be noted that step 3 must end with a stop condition. if a start condition is issued during or at the end of step 3 (instead of a stop condition) the device will abort the nonvolatile register program and remain at step 2. if the operation is aborted with a start condition, the master must issue a stop to put the device into standby mode. figure 10. block lock protect bits and protected addresses 7012 frm t02 figure 11. pp pin and ppen bit functionality 7012 frm t03 bl1 bl0 protected addresses array location X24F128 0 0 none no protect 0 1 3000h - 3fffh upper 1/4 1 0 2000h - 3fffh upper 1/2 1 1 0000h - 3fffh full array pp ppen memory array not lock block protected memory array block lock protected block lock bits ppen bit 0 x programmable protected programmable programmable x 0 programmable protected programmable programmable 1 1 programmable protected protected protected
X24F128 11 absolute maximum ratings* temperature under bias X24F128.....................................?5 c to +135 c storage temperature ........................?5 c to +150 c voltage on any pin with respect to v ss .................................... ?v to +7v d.c. output current ..............................................5ma lead temperature (soldering, 10 seconds) .............................. 300 c *comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. d.c. operating characteristics 7012 frm t06.1 capacitance t a = +25 c, f = 1mhz, v cc = 5v 7012 frm t07 notes: (1) must perform a stop command prior to measurement. (2) v il min. and v ih max. are for reference only and are not 100% tested. (3) this parameter is periodically sampled and not 100% tested. limits symbol parameter min. max. units test conditions i cc1 v cc supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 100khz, sda = open, all other inputs = v ss or v cc ?0.3v i cc2 v cc supply current (program) 3ma i sb1 (1) v cc standby current 10 m a scl = sda = v cc ?0.3v, all other inputs = v ss or v cc ?0.3v, v cc = 5v 10% i sb2 (1) v cc standby current 1 m a scl = sda = v cc ?0.1v, all other inputs = v ss or v cc ?0.1v, v cc = 1.8v i li input leakage current 10 m a v in = v ss to v cc i lo output leakage current 10 m a v out = v ss to v cc v ll (2) input low voltage ?.5 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma v hys (3) hysteresis of schmitt trigger inputs v cc x 0.05 v symbol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (s 0 , s 1 , s 2 , scl, pp) 6 pf v in = 0v recommended operating conditions 7012 frm t04 temperature min. max. commercial 0 c +70 c extended ?0 c +85 c 7012 frm t05 supply voltage limits X24F128 1.8v to 3.6v X24F128? 4.5v to 5.5v
X24F128 12 a.c. operating characteristics (over the recommended operating conditions, unless otherwise specified.) read & program cycle limits 7012 frm t09 power-up timing (4) 7012 frm t10 notes: (4) t pur and t puw are the delays required from the time v cc is stable until the speci?d operation can be initiated. these parameters are periodically sampled and not 100% tested. symbol parameter min. max. units f scl scl clock frequency 0 100 khz t i noise suppression time constant at scl, sda inputs 50 100 ns t aa scl low to sda data out valid 0.3 3.5 m s t buf time the bus must be free before a new transmission can start 4.7 m s t hd:sta start condition hold time 4 m s t low clock low period 4.7 m s t high clock high period 4 m s t su:sta start condition setup time (for a repeated start condition) 4.7 m s t hd:dat data in hold time 0 m s t su:dat data in setup time 250 ns t r sda and scl rise time 1 m s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 m s t dh data out hold time 300 ns symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 5 ms a.c. conditions of test 7012 frm t08 input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 equivalent a.c. load circuit 7012 ill f14.1 5v 1.53k w 100pf output
X24F128 13 symbol table waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance the program cycle time is the time from a valid stop condition of a program sequence to the end of the internal erase/program cycle. during the program cycle, the X24F128 bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. bus timing 7012 ill f15 t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high program cycle limits 7012 frm t11 symbol parameter min. typ. (5) max. units t wr (6) program cycle time 5 10 ms 7012 ill f16 scl sda 8th bit word n ack t wr stop condition start condition guidelines for calculating typical values of bus pull-up resistors 7012 ill f17 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k w ) bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k w bus timing notes: (5) typical values are for t a = 25 c and nominal supply voltage (5v). (6) t wr is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the nonvolatile write operation.
X24F128 14 packaging information 3926 fhd f01 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
X24F128 15 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.386 (9.80) 0.394 (10.01) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.012 (0.30) 0 C 8 x 45 3926 fhd f26 16-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 16 places footprint
X24F128 16 ordering information part mark convention device X24F128 x x -x v cc range blank = 1.8v to 3.6v 5 = 4.5v to 5.5v temperature range blank = 0 c to +70 c e = ?0 c to +85 c package p = 8-lead plastic dip s = 16-lead soic blank = 1.8v to 3.6v, 0 c to +70 c 5 = 4.5v to 5.5v, 0 c to +70 c e5 = 4.5v to 5.5v, ?0 c to +85 c X24F128 x x limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue production and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. X24F128 p = 8-lead plastic dip s = 16-lead soic e = 1.8v to 3.6v, ?0 c to +85 c
X24F128 17 notes
X24F128 18 u.s. sales offices corporate of?e xicor inc. 1511 bu ckeye drive milpitas, ca 95035 phone: 408/432-8888 fax: 408/432-0640 e-mail: info@smtpgate.xicor.com northeast region xicor inc. 1344 main street waltham, ma 02154 phone: 617/899-5510 fax: 617/899-6808 e-mail: xicor-ne@smtpgate.xicor.com southeast region xicor inc. 100 e. sybelia ave. suite 355 maitland, fl 32751 phone: 407/740-8282 fax: 407/740-8602 e-mail: xicor-se@smtpgate.xicor.com mid-atlantic region xicor inc. 50 north street danbury, ct 06810 phone: 203/743-1701 fax: 203/794-9501 e-mail: xicor-ma@smtpgate.xicor.com north central region xicor inc. 810 south bartlett road suite 103 streamwood, il 60107 phone: 708/372-3200 fax: 708/372-3210 e-mail: xicor-nc@smtpgate.xicor.com south central region xicor inc. 11884 greenville ave. suite 102 dallas, tx 75243 phone: 214/669-2022 fax: 214/644-5835 e-mail: xicor-sc@smtpgate.xicor.com southwest region xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw@smtpgate.xicor.com northwest region xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw@smtpgate.xicor.com international sales offices europe northern europe xicor ltd. grant thornton house witan way witney oxford ox8 6fe uk phone: (44) 1933.700544 fax: (44) 1933.700533 e-mail: xicor-uk@smtpgate.xicor.com central europe xicor gmbh technopark neukeferloh bretonischer ring 15 85630 grasbrunn bei muenchen germany phone: (49) 8946.10080 fax: (49) 8946.05472 e-mail: xicor-gm@smtpgate.xicor.com asia/pacific japan xicor japan k.k. suzuki building, 4th floor 1-6-8 shinjuku, shinjuku-ku tokyo 160, japan phone: (81) 3322.52004 fax: (81) 3322.52319 e-mail: xicor-jp@smtpgate.xicor.com mainland china taiwan/hong kong xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw@smtpgate.xicor.com singapore/malaysia/india xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw@smtpgate.xicor.com korea xicor korea 27th fl., korea world trade ctr. 159, samsung-dong kangnam ku seoul 135-729 korea phone: (82) 2551.2750 fax: (82) 2551.2710 e-mail: xicor-ka@smtpgate.xicor.com ( ) = country code xicor, inc., marketing dept. 1511 buc keye drive, milpitas, california 95035-7493 tel 408/432-8888 fax 408/432-0640 rev. 4 3/96 stock# xx-x-xxxx xicor product information is available at: http://www.xicor.com

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